Speakers
Description
Increasing the utility of Noisy Intermediate-Scale Quantum (NISQ) devices requires efficient error mitigation, particularly for Variational Quantum Algorithms (VQAs) where accurate expectation values dictate gradient reliability. In this work we propose a novel Cyclic Layout Permutations based Zero Noise Extrapolation (CLP-ZNE) protocol for such a task. The method leverages the inherent non-uniformity of gate errors in NISQ hardware to extrapolate the expectation value, averaged over cyclic circuit layout permutations, to the level of zero noise. Crucially, we prove that this method cancels all linear-order noise contributions.
In contrast to the previous layout permutation based approaches scaling as $O(n!)$ for $n$ qubit circuit, CLP-ZNE requires execution of only $O(n)$ and at most $O(n^2)$ different circuit layouts for circuits of one-dimensional and arbitrary connectivity, respectively. When benchmarked against noise channels modeling the IBM Torino quantum computer, the method reduces a typical error in expectation values of $n=12$ qubit circuits by an order of magnitude, outperforming standard unitary folding ZNE. Demonstrating robust mitigation of both depolarizing and $T_1/T_2$ relaxation processes, CLP-ZNE provides a highly scalable, hardware-aware pathway to improve VQA trainability on present-day NISQ hardware.
| Topic | Machine learning techniques for experimental quantum information science |
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| Additional Topic | Quantum variational circuits and their applications |